1. Technical Field
The present invention relates to a system and method for generating fast instruction and data interrupts for processor design verification and validation. More particularly, the present invention relates to a system and method for invalidating translation entry valid bits in order to provoke storage interrupts during test case execution.
2. Description of the Related Art
Processor testing tools exist whose goal is to generate the most stressful test case for a processor. In theory, the generated test case should provide maximum test coverage and should be interesting enough to stress various timing scenarios on the processor. The whole technology of these tools sits in the logic of building these test cases.
One aspect of design verification and validation is testing interrupt logic in conjunction with address translation table arrays and parity checks, such as with a translation lookaside buffer (TLB). A TLB includes translation entries for translating virtual addresses to real addresses. Each translation entry includes a “valid bit” that indicates whether the entry's translation is actually valid.
Verifying and validating a processor using test cases typically includes three stages, which are 1) test case build stage, 2) test case execution stage, and 3) validation and verification stage. A challenge found is generating a sufficient amount of interrupts to test the interrupt logic in conjunction with address translation table arrays and parity checks regardless of the test case itself. Instead, existing art generates a large amount of individual test cases that are tailored to test the interrupt logic in conjunction with address translation table arrays and parity checks. This approach requires a significant amount of upfront build time, which reduces overall testing time.
What is needed, therefore, is a system and method for generating a large amount of interrupts, independent of a test case under execution, to sufficiently test a processor's interrupt logic in conjunction with address translation table arrays and parity checks.